A dual-structure analytical framework composed of the chip-economy inverted pyramid and the chip-design-complexity inverted pyramid, which reveals the extreme asymmetry of the global semiconductor supply chain’s fine-grained division of labor and the bilateral lock-in between the US and China; according to SIA estimates, the economic cost of full autonomy for either side amounts to a one-time investment of approximately $900–1,200 billion and would drive global chip prices up 35–65%.
The Framework As It Stands
This section is compiled from the research draft: the original framework’s structure, terminology, and key expressions are preserved, with editorial bridging and external fact-annotations; diagrams were drawn by the compiler following the original framework’s structure.
Entry Point: The White House June 2021 Resilient Supply Chains Report
In June 2021, the Biden administration published the Building Resilient Supply Chains report, integrating the views of more than 10 federal agencies — including Commerce, Energy, Defense, and HHS — and hundreds of experts, released in two phases (Part 1: chips/batteries/critical minerals/pharmaceuticals; Part 2 in February 2022: defense/public health/ICT/energy/transportation/agriculture). The report for the first time elevated supply chains to national security strategy, marking a shift in the globalization model from “just-in-time” (production on demand / profit maximization) to “just-in-case” (redundancy / security first). The framework holds that this switch will roll back global productive efficiency and create structural inflation — The Stagflation Risk Framework provides a dedicated analysis of the macro transmission mechanism of this switch.
The Chip-Economy Inverted Pyramid (Market Scale vs. Leverage in Inverse Proportion)
A single chip, from design to installation in a finished product, consumes 300+ raw materials, passes through 50+ categories of precision equipment, takes 100+ days, and crosses 70+ national borders; a typical US semiconductor company has 16,000+ suppliers (7,300 domestic, 8,500 overseas). This is the most precise ecosystem accumulated over more than 50 years.
Market scale increases from the bottom tier to the top, but the leverage ratio runs in the opposite direction:
| Tier | Market Scale (approx. 2021) | Leverage |
|---|---|---|
| EDA tools | $10–11 billion | 1000x+ (leverages $10 trillion+) |
| IP licensing | $5 billion | Extremely high |
| Chip design | $250+ billion | High |
| Chip manufacturing | $500+ billion | Moderate |
| Chip applications | $10 trillion+ | 1x |
EDA collapse = collapse of the entire chip economy — the framework identifies this as the greatest blind spot in China’s strategy.
The US EDA Big Three (Synopsys / Cadence / Siemens EDA) together hold 77% of the global market and over 95% in China; adding ANSYS + Keysight to form a Big Five raises the monopoly share even further. The US cut-off of EDA tools to Huawei is more lethal than cutting off chips — it directly decapitates long-term design capability. Chinese EDA companies (representative: Huada Jiutian) can only achieve breakthroughs in point tools and cannot rise comprehensively — the market ecosystem is already dead-locked.
The Chip-Design-Complexity Inverted Pyramid
| Complexity Level | Type | Dominant Party |
|---|---|---|
| Founding tier (Philosopher) | Instruction set architecture (X86 / ARM / RISC-V) | US / UK |
| Master tier | Microprocessor architecture (CPU/GPU) | US |
| Distinguished tier | Logic chips (MCU/FPGA) | US / Europe |
| Excellence tier | Memory chips (DRAM/Flash) | Korea (dominant) |
| Craftsman tier | Analog, discrete, photonic, sensor | China has a relatively solid base |
In 2020, China had 2,218 semiconductor design companies (up 438 from 2019), but only 289 with annual revenues exceeding CNY 100 million and only 29 with more than 1,000 employees; overall concentration remains at the “craftsman tier” and “excellence tier.” Instruction set architecture is the foundation of all chips — The Rebellion Against Comparative Advantage in its most extreme form in the semiconductor domain. X86 (Intel/AMD) and ARM (mobile monopoly) carry heavy historical baggage; RISC-V (originated by Krste Asanović et al. at UC Berkeley from 2010 onward, with the RISC-V Foundation established in 2015) is the only path by which China might leapfrog — minimalist (40-odd instructions) / clean / modular / extensible / open-source / no historical baggage / perfectly suited to IoT + AI + autonomous driving.
The US-China Bilateral Lock-In
US: accounts for 64% of global chip design and only 12% of chip manufacturing, yet captures approximately 50% of global profits (global semiconductor market in 2020 was approximately $440.4 billion).
China: imports 100+ billion in memory), accounting for approximately 35% of global chip consumption, with manufacturing concentrated in low-end process nodes.
SIA estimate: if each side pursues full autonomy, one-time investment of 350–420 billion, China: 45–125 billion thereafter, and global chip prices rising 35–65%. The hardware chip dependencies in China and US Payment Systems constitute an equivalent lock-in logic.
flowchart TD A["White House June 2021 Resilient Supply Chains Report<br/>Integrating 10+ agencies + hundreds of experts"] --> B["Globalization Model Switch<br/>just-in-time → just-in-case"] B --> C["Cost: Global Structural Inflation<br/>Chip prices +35–65%<br/>One-time investment $900–1,200 billion"] A --> D["Current State of the Chip Industry<br/>50+ year precision ecosystem<br/>300+ materials / 100+ days / 70+ borders"] D --> E["Chip-Economy Inverted Pyramid<br/>EDA $10 billion → Applications $10 trillion+<br/>Base-layer leverage 1000x+"] D --> F["Chip-Design-Complexity Inverted Pyramid<br/>Founding tier (ISA)<br/>to Craftsman tier (Analog)"] E --> G["US EDA Big Three Dead Lock<br/>Synopsys/Cadence/Siemens<br/>77% global / 95%+ China"] F --> H["China's weak points: ISA + EDA + high-end logic<br/>US's weak points: manufacturing + dependence on China's consumer market"] G --> I["US Weaponizes EDA Against China<br/>Cut-off of Huawei = long-term capability decapitation"] H --> J["US-China Bilateral Lock-In<br/>Neither can leave the other<br/>Decoupling: mutually assured losses"] I --> K["China's Strategic Backup: RISC-V<br/>Open-source + minimalist + modular + extensible<br/>Targeting IoT + AI + autonomous driving"] J --> K K --> L["Leapfrog Window<br/>15–30 year long campaign<br/>Abandoning the X86/ARM historical path"]
Compiler’s Perspective
Coordinates: Category = China and Great-Power Rivalry / axis_h = Shu / axis_v = Its Place in the Whole
Connection Layer
The two inverted pyramids establish a counterintuitive priority: EDA’s market scale is only 10-trillion chip applications market and overlook EDA, only to discover when a supply cutoff occurs that the $10-billion cornerstone has been weaponized. Similarly, those using “how many design companies / how many tapeouts” to assess China’s chip self-sufficiency progress will systematically underestimate the risk that “founding tier not self-sufficient = design capability can be zeroed out by remote control at any time” — 2,218 design companies go to zero overnight under an EDA cutoff.
Proprietary Increment
The framework’s proprietary criterion: the design cost of a 5nm system-on-chip is approximately 1 billion at 3nm — while a single ASML EUV lithography machine costs $150 million, making the manufacturing-side constraint visible; but EDA software lock-in is a hidden leverage, and a single quarter of supply cutoff can halt all in-progress projects dependent on Synopsys/Cadence. This means: when assessing the intensity of the chip war, the immediate-impact weight of an EDA ban should rank higher than that of a lithography-machine ban — because EDA software licenses are renewed monthly/annually, whereas lithography machine inventory can sustain operations for 2–3 years.
See Also
- The Rebellion Against Comparative Advantage
- China and US Payment Systems
- The Stagflation Risk Framework
- The Dollar Crisis of Emerging-Market Currencies
Sources
- Compiled draft z-0027 · archived 2026-07
- White House, Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-Based Growth (2021-06-04), whitehouse.gov
- SIA, Strengthening the Global Semiconductor Supply Chain in an Uncertain Era (2021-04), semiconductors.org
- RISC-V International, risc-v.org; RISC-V Foundation established 2015